A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology

This paper presents a novel low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back gate of the stacked independent-gate FinFET devices. Furthermore, these stacked transistors increase the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters. The characteristics of this cell are evaluated by device/circuit level simulations using Sentaurus device TCAD device simulator at different supply voltages and in the presence of process variations. The results indicate that the proposed SRAM cell reduces the static power by 37% and 56%, respectively, while providing comparable and even higher static noise margins, as compared to the 6T and 8T FinFET-based SRAM cells.