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Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew
Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew
2013
Shunsuke Shimazaki
S. Taga
Tetsuya Makita
Naoya Azuma
Noriyuki Miura
Makoto Nagata
Keywords:
Emulation
Clock skew
Digital electronics
Electronic engineering
CMOS
Digital clock manager
Computer science
Electrical engineering
cmos digital circuits
Correction
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