Impact of Noise and Device Variation in Nanoscale Ferroelectric Finfets Towards Its Applicability in Neuromorphic Computing and Artificial Intelligence

This paper reports an elaborate analysis and modelling of nanoscale variability in ferroelectric (FE) FinFET memory transistors. FE FinFETs with 10nm Hf0.5Zr0.5O2 gate insulator is fabricated using a gate-first process. Multi-fin short-channel devices exhibit pronounced FE switching due to reduced channel-side trapping and prominent inter-domain coupling, which is explained with a compact model for multiple domain FE capacitors. All devices at short (50nm) gate length exhibiting FE switching, with the champion device showing a large 4.8V memory window. With highly linear and symmetric multi-level characteristics, FE FinFETs is suitable for deep neural network applications. Neuromorphic-oriented physics-based compact model for FE FinFET is developed and applied to macro-level online training simulation. 96.3% MNIST image classification accuracy is achieved even in the presence of experimentally calibrated device-to-device and cycle-to-cycle variability.