Surface electrical conduction measurement of Si (100) film of silicon-on-insulator wafers

This paper discusses an investigation into the surface electrical conduction of Si(100) film in the Silicon-on-Insulator (SOI) wafer. Controlling the gate voltage of the so-called `pseudo-MOSFET', which is a kind of MOSFET and in which the gate voltage is applied to the substrate of SOI wafers, can reduce the contribution from conduction inside the silicon film. The drain current and the resistivity of the silicon film were measured at the cut-off region in drain current–gate voltage (Id–Vg) characteristics of the pseudo-MOSFET. The experiment shows that the drain current at this region of the HF-treated sample becomes much higher than that of one before HF treatment. Compared with a calculated approximation, this high drain current cannot be explained by the existence of the inversion layer caused by the pinning at the silicon film surface. Hence, it must be due to the surface electrical conduction.