A 128 kb SRAM with soft error immunity for 0.35 /spl mu/m SOI-CMOS embedded cell arrays

Summary form only given. Embedded cell arrays are more suitable for high-performance ASICs rather than gate arrays, because they can integrate high-quality building blocks such as high-density memories and optimized analog circuits together with digital logic circuits. This paper describes a 128 kb synchronous SRAM with body-fixed structure for embedded cell arrays using a 0.35 /spl mu/m SOI-CMOS process. The circuit performance and the soft error rate of the SRAM were measured and compared with those of a 128 kb SRAM with floating-body configuration.