0.6 V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization

Increasing dc offset voltage and 1/ f noise becomes a serious problem in scaled complementary metal oxide semiconductor (CMOS) technologies. In particular, device deviation causes a large dc offset voltage in an amplifier, and the circuit design with a low-power supply voltage becomes difficult. In this paper, a noise reduction technique and calibration techniques for device deviation with a low supply voltage are presented. The proposed techniques achieve autozeroing and chopper stabilization without using analog switches. The low-noise amplifier fabricated by 0.18 um CMOS technology was measured with a 0.6 V supply, and achieved 130 µW power consumption, 89 nV/√Hz input noise (at 100 Hz).