A Design Methodology for the Next Generation Real-Time Vision Processors

In this work we present a methodology to design the next generation of real-time vision processors. These processors are expected to achieve high throughput with complex applications, under real-time embedded constraints time, fault-tolerance, silicon area and power consumption. To achieve these goals, we propose the fusion of two key concepts: the Focal-Plane Image Processing FPIP and the Many-Core architectures. We show the concepts and ideas to build-up a methodology able to offer both design space exploration, and a customized programming toolchain for the final architecture. We present implementation details and results for working parts of the framework, and partial results and general comments about the work-in-progress.