Application of Low Power Pulse Triggered Flipflop Based On Signal Feedthrough Scheme in Enhanced Scan Design

Testing delay faults in sequential circuits is significantly more difficult than testing delay faults in combinational circuits. This is because testing for a delay fault requires the application of a pair of test vectors in an at-speed manner and application of an arbitrary vector pair is not possible to non-scan or standard scan sequential circuits. To solve this problem we are using memory elements that can store two bits of state instead of just one. Such flipflops are called enhanced scan flipflops.. This paper proposing an enhanced scan design using an explicit type pulse triggered flipflop based on signal feed through scheme. The low-power flip-flop design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance.