Single event upset resistant SRAM (static random access memory)

The invention relates to a single event upset resistant SRAM (static random access memory), comprising a single-bit storage array built with basic storage units, a line pre-decoding circuit, a line secondary-decoding circuit, a column pre-decoding circuit, a line secondary-decoding circuit, a sensitive amplifying circuit, a timing sequence control circuit, a read-write control circuit, an IO (input/output)circuit, and an EDAC (error detection and correction) clock control circuit, an EDAC encoding circuit, an EDAC encoding circuit, and an EDAC input/output circuit; the EDAC circuitry and SRAM circuitry are designed in a whole, the internal timing sequence control circuit is reasonably designed, all reading, writing, error detecting and correcting, encoding and decoding, and sampling of data are finished in a clock period, data reading-writing access time is shortened, and the timing sequence requirement for work clock frequency not less than 200 MHz is met.