Sub-0.3V CMOS neuromorphic technology and its potential application

The aim of this paper is to present a sub-0.3 V neuromorphic technology developed for spiking neural network design and its potential application. The main properties of the developed ultra low power (ULP) artificial neuron are first recalled. A description of ULP synapses follows that includes the plasticity scheme. The neuromorphic toolbox is then used to design a basic circuit allowing oriented edges classification. The circuit is made of 40 neurons and 108 plastic synapses, its consumed silicon core area is 0.025 mm2 and the overall power consumption of 5 nW. Finally, the deployment of the technology within an industrial context to fabricate highly energy efficient Spike-based visual sensor is discussed.