Field effect transistor of hybrid conduction mechanism

The invention discloses a field effect transistor with a hybrid conduction mechanism, belonging to the field of field effect transistor logic devices in CMOS (Complementary Metal-Oxide-Semiconductor) ultra-large-scale integration (ULSI) circuits. The field effect transistor of the hybrid conduction mechanism comprises a source electrode, a drain electrode, a channel region and a control grid, wherein the source electrode comprises a tunneling source electrode and a diffusion source electrode. For an N-type device, a source region comprises a P-type tunneling source electrode which is shallower in junction depth and an N-type diffusion source electrode which is deeper in junction depth. For a P-type device, a source region comprises an N-type shallow tunneling source electrode and a P-typedeep diffusion source electrode. The tunneling source electrode and the diffusion source electrode are subjected to potential lead-out on the source electrode at the same time; the doping type of thedrain electrode is same as that of the diffusion source electrode at the source end, and the doping type of a substrate is same as that of the tunneling source electrode. Compared with the traditional TFET (Tunneling Field Effect Transistor), the field effect transistor disclosed by the invention can be used for effectively increasing the conduction current of a device and improving the driving capability of the device.