Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

In this chapter, we examine the design process of a network on-chip (NoC) for a high-end commercial system on-chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required performance. Our design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow timing constraints were used, we demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process. In order to evaluate the different alternatives, we report the synthesis results of a design that meets the actual throughput and timing requirements of the commercial SoC. According to our findings, the proposed technique offers up to 40% savings in the total router area, 49% savings in the inter-router wiring area, and a 16% reduction of total power for our target router architecture.