PERFORMANCE ANALYSIS OF FLASH ANALOG TO DIGITAL CONVERTER WITH TRACK AND HOLD CIRCUIT USING CADENCE PSPICE

This paper proposes a new low power design technique for high speed flash analog to digital converters. This low power design technique will reduce the power consumption of flash A/D converters by 50% reduction of the number of comparators in the circuit. The outputs from the comparators are in thermometer code, an encoder is used to convert this thermometer code to binary code. A novel track and hold circuit which is introduced in this technique. The flash A/D converter using the proposed T/H circuit can realize the same accuracy with the conventional one. Its power consumption is evaluated by CADENCE PSPICE simulations. It is confirmed that the proposed technique can save 35% of power consumption compared with the conventional one.