A New High-k Transistor Technology Implemented in Accordance with the 55nm Design Rule Process

NEC Electronics has developed a transistor that delivers low current leakage, high performance and a significant reduction in the manufacturing processes. These solutions have been achieved by establishing a threshold voltage control technology to control the work function by applying a trace of hafnium to the gate insulation film of a transistor. This paper introduces the 55nm (nanometer) node design rule CMOS process technology, "UX7LS" which combines the above new transistor technology and the immersion lithography technology. UX7LS enables a wide variety of applications to be covered with a single transistor structure by controlling the threshold voltage, between 0.3V to 0.5V. Moreover, a performance increase of approximately 20%, a process decrease of maximum 15% and scaling down of the SRAM cell size to 0.446μm 2 have been achieved compared to the performance of transistors that conform to the 65nm design rule.