High performance SOI technology for sub-45nm gate length CMOS manufacturing

Partially depleted (PD) SOI technologies are mature for production of high speed, low power microprocessors. The paper highlights several challenges found during the course of development of a PD 90nm SOI technology. The technology features highly advanced transistors using strained Si and a gate length of sub 45nm with a nine layer low k backend. By optimizing the strained Si process and overall processing we have achieved yield equal than conventional technologies but with higher performance. The technology was developed for the 64bit Opteron and Athlon 64 microprocessors.