A high-level analysis of a multi-core vision processor using SystemC and TLM2.0

Vision Processors are integrated circuits with the aim to put together sensors and processing elements at the same chip. There are several constraints a designer may take into account when developing a vision processor: available technology, power consumption, thermal management, fault tolerance, speed, silicon area and application-specific needs. Most of these vision processors are based on analog circuits and can perform only low-level processing, like filtering and contrast adjustment. Digital processing elements can allow for more programmability in such systems, however, the approaches found in the literature do not explore the integration of sensor and processing elements in an efficient way. In addition, it is envisioned that vision processors can take advantage of the recent Multi/Many-Core advances. In this work, a full integration is analyzed, exploring the spatial distribution of sensors and processors. All the design blocks were developed using SystemC language with TLM2.0 standard, in order to allow for a better ESL analysis. The exploration of pure LT and mixed LT/AT models is used for extract information about parallelism in data transfer and operations. An application with some well-known algorithms is analyzed for a variable number of cores, in order to validate the tool-set and the methodology used.