Materials and processes issues in fine pitch eutectic solder flip chip interconnection

New product designs within the electronics packaging industry continue to demand interconnects at microscopic geometry, both at the integrated circuit (IC) and supporting board level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by competitive manufacturing costs and the need for higher volume and robust production capabilities. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology (SMT) and combines an under bump metallisation (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition, have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of such bumps at different geometries. The effect of precise control of the tolerances of squeegees, stencils and wafer fixtures was examined to enable the optimisation of the materials, processes and tooling for reduction of bumping defects.