Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC

A modified dynamic comparator is proposed and compared in this paper. A dynamic comparator consists of a low gain amplifier connected to a latch circuit. The inputs are amplified during the evaluation period and the outputs are latched during the regeneration time. The proposed dynamic comparator is fast and consumes less power. At a clock frequency of 1.25GHz and 100mV ΔVin, the delay is 176.71ps and average power consumption is 119.81μW for a supply voltage of 1.8V. The calculated maximum PDP is 24.53 f. The proposed dynamic comparator is suitable for an efficient low power and high speed Flash ADC. The circuits are simulated in cadence virtuoso spectre with 180nm SCL technology.