A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter

A complete Digital Front-End (DFE) processor for 60 GHz polar transmitter is presented. It avoids supply modulating, RF limiters, and AM detection circuits, compared to traditional analog-centric polar transmitter architectures. The front-end processor consists of i) a poly-phase Cascaded Integrator-Comb (CIC) filter for spectrum shaping; ii) parallel COordinate Rotation DIgital Computer (CORDICs) for rectangular-to-polar conversion; and iii) Power Amplifier (PA) non-linearities pre-distortion units using Look-Up Tables (LUTs). It is designed in two-phase latch-based pipeline to achieve a throughput of 4×1.76 Gsps. Implemented in a standard 28 nm CMOS technology, the DFE processor occupies 0.031 mm 2 and consumes 39mW from 0.9V supply. This result outperforms previously reported architectures.