Tensile Contact Etch Stop Nitride for nMOS Performance Enhancement: Influence of the Film Morphology

We have studied different nitride processes to provide the best tensile layer for this application. Several Plasma Enhanced Chemical Vapor Deposition techniques, with one or two plasma frequencies (PECVD 1F or 2F), and a furnace Atomic Layer Deposition (ALD) process have been evaluated. Deposition on full sheet wafers allowed to characterize the main physical and chemical properties. In particular, the mechanical stress σ was measured by curvature method. Moreover, the sidewall step coverage (SSC) was evaluated by SEM / TEM cross section (see Table 1). The best step coverage is obtained for ALD (better than 95%) layers while PECVD 2 F (75%) presents an intermediate situation compared to PECVD 1F (55%). In parallel, the same films with different stress σ and thicknesses e distributed between 350A and 500A were tested on full flow device wafers. For each case, we measured the Ion and Ioff currents for transistors with different length (L) and a fixed width W=1μm. We then estimated the gain of Ion at Ioff =10 nA compared to a stress less reference. The performance improvement is typically proportional to the curvature created by the CESL. Therefore, it must be proportional to the product stress σ by thickness e. On Figure 1, we present for each layers, the Ion gain as a function of this product. It is clear that for a given σ*e, ALD nitrides generates more improvements than PECVD films. On Figure 2, we present the Ion improvement as a function of σ*e*SSC. In this case, the distance to the linear model is significantly improved with a R = 0.96 compared to R = 0.82 in Figure 1. As a consequence, The SSC has to be considered with σ and e to describe the gain obtained for different nitrides Thanks to these observations, we suggest a model to describe the mechanical impact of the CESL on the Si channel. As illustrated in Figure 3, especially on small devices, the tensile nitride film acts as tensile strings on the sidewall of the transistor. These strings generate a strain in the Si channel proportional to it’s surface (pressure effect). A lower step coverage yields to a lower strings concentration and a lower strain in the channel. This model is validated with both mechanical simulations studies and the electrical data of reference [5].