The Secured AES designs against Fault Injection Attacks: A comparative Study

To protect the Advanced Encryption Standard (AES) against physical attacks known as fault injection attacks various fault detection schemes have been proposed. In this paper, a comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. In the considered study we implement, separately, the hardware, the temporal and the information redundancy for the 32-bit AES. These schemes are implemented on the Virtex-5 Xilinx FPGA board in order to evaluate their efficiency in terms of area, time costs and fault coverage