Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive

The markets trends in the automotive industry of efficiency, safety and standardization, demand an increase in system performance (e.g., system frequency or by using multi core architectures) in microcontrollers for automotive powertrain applications. Since embedded nonvolatile memory is an essential part of such an SoC, the memory read speed must increase at the same rate to achieve best possible overall system performance. A further trend is that memory size is increasing with every new technology node to support complex algorithms required for real-time automotive applications. Larger memory sizes lead typically to an increase of the bitline (BL) capacitance, which is one of the most critical parameters for read performance of a memory array.