Computational nano OPC DFM for LV Fin-type SRAM

Design For Manufacturing (DFM) where the state-of-the-art nano-devices of the sub-20nm node to a subject, for each of the technology has been intricately sophisticated, comprehensive optimization to predict the performance of the device came become very important. [1] To get effective solutions on these subjects, one of the lithographic key is a nano Optical Proximity Correction (OPC) control with SMO technology, and another is TCAD approach using the most advanced computer simulations. And, it is very important to obtain DFM solutions by integrating both. On the other hand, to meet the needs of low-voltage drive and the characteristic variability reduction, in order to obtain a state-of-the-art device performance, the Fin-type transistors are introduced globally as the mainstream because of wider process control margin. This paper, from the point of view of the sub-20nm node DFM, the simulation are conducted on ArF-imm. technology with SMO in SPT, DPT and QPT on TachyonTM [2], and the guideline of design rules are obtained. Furthermore, the simulated transistor pattern shape are directly migrated into TCAD process flow on HyENEXSSTM [3]. Then calculated I-V characteristics on 6 transistors under the various parameters on TCAD, and finally summarized Static Noise Margin (SNM) of SRAMs. Here, various parameters that determine the performance of SRAMs (Fin width, height, angle, dopant concentrations, electric field strength, work function, drive voltage, and operation speed) are intentionally varied and calculated on the TCAD. This computational method is highly sophisticated DFM technology to predict for the leading-edge nano-devices toward for the sub-20nm nodes era [4] [5] [6] [7] .