System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics

Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for a high speed serial interface to be used in automotive Electronic Control Units. The transmitter has been designed in a standard 28 nm technology and features feed-forward equalization (FFE) with 8 taps (1 pre- and 6 post-cursors), whose strength is programmable with 16 discretization steps. It is shown that the parasitic inductance on the supply terminals degrades the performance in terms of jitter and SNR and tends to hamper the benefits of FFE. When the value of these inductances is minimized, system-level models of the transmitter reproduce quite well time-consuming transistor-level simulations.