Design of High-Speed Binary Counter Architecture for Low-Power Applications

This chapter presents a design of high-speed binary counter architecture using clock gating for low-power applications. Clock gating techniques enables in improving the latency and power dissipation of proposed binary counter. The latency of proposed architecture is lower as compared to conventional architecture, which shows that the proposed design can be operated at high input frequencies. The proposed binary counter design of 4-, 8-, and 16-bit has been built by Verilog HDL code and simulated using Questa Simulator of Mentor Graphics. For synthesis of proposed design, LeonardoSpectrum tool by mentor Graphics is used and synthesis of it is based on CMOS process TSMC 0.35 µm, Spartan 6, and Spartan 3E FPGA. The Semicustom physical layout for Proposed 8-bit counter architecture using 350-nm Standard CMOS process is also obtained in this work.