F4E prototype of a chopper digital integrator for the ITER magnetics

Abstract The main goal of this work is to demonstrate that a digital integrator based on the signal chopping concept is capable of attaining the ITER requirements. In particular, the ITER magnetics diagnostic requires a maximum flux drift of 500 μV s/hour, among other specifications, for the signal integrators. As of today, known commercial integration modules do not fully comply simultaneously with all ITER magnetics requirements. A first phase of prototyping, presented in this work, comprises the development and testing of four design variants. Combinations of a SAR ADC (AD7960) and a Delta-Sigma ADC (ADS1675) with different analog front ends were used for the corresponding integrator prototypes. The designs have a common interface to an FPGA based system that receives the data acquired during the tests and streams it through a GbE link to a PC, where real-time digital integration of the signals is performed using the MARTe control framework. The GbE network also acts as the interfacing medium for the data archiving, through the connection of the integrator prototypes under test to an MDSplus based environment. This paper presents the integrator prototype designs developed and tests done so far.