A Typical-case Design Methodology Mitigating Timing Constraints and its Evaluation via Co-Simulations

The deep submicron semiconductor technologies have increased process variations. They make worst– case designs impossible. This is because larger variations require larger design margins. In order to realize robust designs, we have to design LSIs by considering typical-cases rather than worst cases. We are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In order to evaluate the CTV, we have to consider circuit delay. We build a co-simulation environment by combining gate level simulation with architectural level simulation. We evaluate the CTV and its enhanced techniques by the co-simulation environment.