Self‐aligned bipolar transistors fabricated by selective etching of polysilicon technology

To fabricate submicrometer transistors practical for LSI by conventional photolithography with a minimum pattern width of 1.5 μm, a self-aligned process using a selective etching of polysilicon technology (SEPT) has been developed. Compared with the formation of fine patterns by side etches of overhangs, this process, using an oxide thickness and a diffusion distance as a pattern width, has a high accuracy and reduces the variation of the base voltage (VBE) which becomes an important characteristic when the emitter size is reduced by a self-alignment technique. In this method of self-aligning the base contact and the emitter, a submicron transistor with emitter width of 0.8 μm, base-emitter spacing of 0.4 μm, and the base contact width of 0.3 μm can be fabricated with a mask pattern of 1.5 μm width. By the reduction of the active region, the junction capacitance and the base resistance which affect the high-speed performance have been reduced drastically. A 25-stage, 3-input ECL ring oscillator designed with practical rules of 1.5 μm minimum pattern width and 4.5 μm interconnection pitch has shown a delay of 95 ps (ICS = 0.78 mA). Since this method has a high-dimensional accuracy and reduces the VBE variation which becomes an important characteristic for LSI, it can be used in further scaling.