Detection and reduction of via faults

A methodology for fast detection of via faults is presented. Defective vias in large via chains are detected by subsequent use of a parametric tester for resistance measurements, a CD-SEM for voltage contrast inspection and defect localization, and focused ion beam (FIB) preparation for failure analysis. Short loop experiments were applied to fabricate large via chains in a short cycle time. The method was applied for optimizing the lithography process for via layers. As a result, the density of yield-limiting blob defects was reduced.