A single-event-hardened CMOS operational amplifier design

Novel RHBD techniques are described that utilize charge sharing to mitigate single-event voltage transients in a folded cascode operational amplifier. These techniques are analyzed using a new layout aware single-event model with the Cadence Spectre circuit simulator. The techniques are applied in each of the three stages of an operational amplifier (op amp). The sensitive node active charge cancellation (SNACC) technique is applied to the bias circuit and extended to protect multiple sensitive nodes. This technique is shown to provide a 5X reduction in error energy measured at the amplifier output at the cost of increased sensitive area. The differential input stage and the high-gain single-ended cascode output stage of the amplifier are hardened using differential charge cancellation (DCC) layout techniques that promote charge sharing. These hardening techniques are shown to provide up to orders of magnitude reductions in single-event error energies as measured at the op amp output and reductions in sensitive area of more than 15% across all LETs simulated.