Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system

Embedded multi-core systems are gaining popularity for many embedded applications. Compared to the multi-core design for general purpose high performance computing, the memory design for an embedded multi-core processor should be customized and adapt to embedded application's characteristics, because it usually has significant impact on the system performance. In this paper, we study a 3D embedded multi-core DSP processor called 3D-iSPA, which is targeted for multimedia applications with two unique design features and leverages 3D DRAM stacking to improve performance. Many memory controller and wider memory data bus are proposed to make better use of the vertical through-silicon-via (TSV). The experimental results shows that duplicating memory controller can provide 10X speedup. The pure wider memory bus, however, has weak impact on the performance due to the limitation of on-chip interconnect. 1