A broadband CMOS amplifier in D band using pole-tuning technique with T-type network

A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of 26 GHz, while consuming a dc power of 62 mW. The saturation output power and the output P 1dB are 8.6 dBm and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm 2 including all testing pads.