Implementation of Digital Filters in Programmable Logic Devices

Recent strides in programmable logic density, speed and hardware description languages (HDL’s) have empowered the engineer with the ability to implement digital signal processing (DSP) functionality within programmable logic devices (PLD’s or FPGA’s). This paper, written for the intermediate DSP engineer or logic designer, begins with an overview of general DSP concepts. Filter design principles as well as specific DSP filter architectures are presented including serial and parallel architectures. Techniques for implementing DSP filters in FPGA’s using VHDL are discussed. Methods of exploiting specific FPGA architectures in order to enhance performance in terms of speed, area and power consumption are presented. Some guidelines are given for evaluating different programmable logic device architectures for DSP designs. The paper culminates with a specific IIR filter design implemented in an FPGA using VHDL.