Improved Split CV Mobility Extraction in 28 nm Fully Depleted Silicon on Insulator Transistors

In this work, we assess the applicability of the well known split CV technique for mobility extraction in 28 nm FDSOI transistors with gate length down to 25 nm using TCAD simulations. We identify the significant bias dependence of the parasitic source/drain resistance and the contribution of the inner fringing capacitance as the main sources of error in the conventional split CV extraction. An improved split CV method, correcting for these parasitics, is demonstrated to accurately extract the effective mobility and its dependence on the gate voltage for devices down to 25 nm gate length. Measurements on 28 FDSOI transistors confirm the insights from the TCAD simulations.