Chip integrated circuits and method of manufacture.

An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.