Methods of Detecting Latent Defects in Cells of the Super-Operative Memory of Microcircuits Used in the Digital Signal Processing Systems

The article reveals the reasons for the low efficiency of modern methods for detecting latent defects in the chips of super operative memory (further, memory chips) used in digital signal processing systems. The first reason is due to the constant decline in technological design standards. The second reason is that modern systems of functional testing the memory chips are not able to detect latent defects in the chips in real time. As a third reason, we can point out the insufficient effectiveness of modern “marching” tests, which are widely used for testing memory chips. In this paper, we propose a complex approach to organizing memory chips testing. The main idea this approach is supporting a close relationship is maintained between the mathematical and topological models of the tested chip. It is this connection that eliminates the first two of the above reasons for the low efficiency of memory chips testing methods. The hardware-software complex, that implements this approach, ensures the maintenance of a unified information environment based on the original hardware-oriented programming language STeeL. To eliminate the third reason mentioned above, a special component “Memory” was implemented as part of complex, which, unlike the well-known implementations, allows you to create functional tests of any complexity. This component implements the version of the “marching” test, which is a short dynamic memory test based on statistics from previous tests. The latter circumstance significantly reduces the total time spent on testing chips.