Design of an 1.8V 12-bit 10MSPS Folding/Interpolation CMOS Analog-to-Digital Converter

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with 1-poly 4-metal n-well CMOS technology. The effective chip area is and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.