Low Power Configuration Logic Block Design Using Asynchronous Static

Low power Configuration Logic Block (CLB) for FPGA is highly desirable in VLSI circuit and system. The CLB is the main block of any FPGA architecture. Each CLB block consists of three static LUT's for implementing NCL logic function. 27 fundamental NCL logic gates are implemented in each LUT. The proposed CLB has 10 inputs and 3 different outputs, each with resettable and inverting variations. There are two operating modes in each CLB, Configuration mode and Operation mode. The NCL FPGA logic element is simulated at the transistor level using 130nm TSMC CMOS process technology. Index Terms— Configuration Logic Block (CLB), Field Programmable Gate Array (FPGA), Look Up Table (LUT), NULL Conventional Logic (NCL).