Old Web
English
Sign In
Acemap
>
Paper
>
Optimizing data flow graphs to minimize hardware implementation
Optimizing data flow graphs to minimize hardware implementation
2009
Gomez-Prado
Ren.
Ciesielski
Guillot
Boutillon
Keywords:
High-level synthesis
Digital electronics
Data flow diagram
Digital signal processing
Common subexpression elimination
Computer engineering
Computer science
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]