A 4-bit Architecture of SEED Block Cipher for IoT Applications

A compact architecture of the 128-bit SEED block cipher is presented in this paper. The proposed architecture uses a 4-bit datapath and therefore requires limited hardware resources. The target of this architecture is ultra-low area devices for IoT and wearable applications. The design was coded using the VERILOG language and the BASYS3 board (Artix 7 XC7A35T) was used for the hardware implementation. The proposed implementation utilizes only 425 FPGA LUTs, 382 FFs and $1024 \times 8$ bits Block RAM and reaches a data throughput of 45 Mbps at 204 MHz clock frequency for encryption or decryption.