A CMOS two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique

This paper describes a two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique. The proposed 12-bit SAR ADC consists of two SAR ADCs connected in parallel, so that the sampling rate can be doubled. The first 12-bit SAR ADC is employed to determine the 12 bits and the second 12-bit SAR ADC utilizes the upper 6-bits of the first one, so that it can determine the lower 6-bits and save switching energy. The proposed two-way time interleaved 12-bit SAR ADC is implemented with a CMOS 180 nm 1-poly 6-metal process. The measurement results demonstrate ENOB of 10.2 bits, SNDR of 62.9 dB, power consumption of 69 μW, INL/DNL of ± 1.8 LSB, and Walden FoM of 5.9 fJ/step.