The implementation of a 2-core, multi-threaded Itanium/spl reg/ family processor

The next generation in the Itanium/spl reg/ processor family, code named Montecito is introduced. The processor has two dual-threaded cores integrated on die with 26.5MB of cache in a 90nm process with 7 layers of copper interconnect. The die is 21.5mm by 27.7mm and includes 1.72 billion transistors. With both cores at full frequency it consumes 100W. The micro-architecture and circuit methodologies are leveraged from the prior Itanium2 processors (E. Fetzer et al., 2005). Improvements include the integration of 2 cores on-die, each with a dedicated 12MB 3rd level cache, a 1MB 2nd level I cache and dual-threading. Susceptibility to soft errors is also reduced and power efficiency improved through low power techniques and active power management.