Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

During the 1980s, a novel nonvolatile memory product was introduced, referred to as flash electrically erasable program-mable read-only memory (EEPROM). The basic operating prin-ciple of the nonvolatile memory device is to store charges in the gate oxide of a metal-oxide semiconductor field-effect transistor (MOSFET). If charges can be stored in the oxide of a MOSFET, the threshold voltage of the MOSFET can be modified to switch between two distinct values, conventionally defined as the erase state and the program state. The terms erase and program are used to denote operations that charge and discharge through ox-ide. The threshold voltage shift between the two states is caused by the storage of charge in oxide. The program state is usually obtained from a channel hot electron, while the erase state uses Fowler-Nordheim (F-N) tunneling through a thin gate oxide. The storage of charges in the gate oxide of the nonvolatile memory device can be realized by surrounding a conducting layer by an oxide. Since this layer acts as a completely electrically isolated gate, this type of device is commonly referred to as a floating gate device.An EEPROM cell containing an n-well and metal-insulator-metal (MIM) capacitor was fabricated using a 0.18 μm stan-dard complementary MOS (CMOS) process. In recent efforts, a stacked metal-insulator-metal (MIM) and an n-well capacitor have been applied to a single polysilicon EEPROM cell in order to increase memory capacity [1-4]. The application of the single polysilicon EEPROM is becoming more popular due to its low process cost and satisfactory reliability [5-7]. Optimal charac-teristics of EEPROM include fast program/erase speed, high endurance performance, and low leakage current. Although the MIM capacitor cell performs well, it requires a large device-size. The n-well control gate cell inherently possesses high junction capacitance and high sheet resistance. In this paper, we propose an EEPROM cell that does not re-quire additional cell area in order to obtain a high capacitance. Additionally, the proposed EEPROM provided a satisfactory control gate coupling ratio contributing to the junction capaci-tance between the control gate and the n-well. Because the n-well depletion capacitor was isolated by shallow trench iso-lation (STI) and the MIM capacitor was located just above the n-well capacitor, the cell containing two capacitors connected in parallel was expected to be very reliable and to provide noise immunity.