Self-starting and overclocking a harmonically mode-locking WRC-FPLD with a dual-loop feedback controller for 10?Gb?s?1 pulse-data transmission

The self-starting and overclocking of a harmonically mode-locked weak-resonant-cavity Fabry?Perot laser diode (WRC-FPLD) with a dual-loop coupled optoelectronic oscillator (COEO) based feedback controller is demonstrated to perform a clock-free pulsed data transmission at 10?Gb?s?1. The WRC-FPLD is considered as the preferred candidate for harmonic mode-locking due to its highly asymmetric cavity architecture, whereby the spontaneous noise can be significantly suppressed without inducing large intra-cavity loss. With the dual-loop COEO configuration, the WRC-FPLD can be boosted to four times of its original modulation bandwidth such that the pulsed carrier quality can be refined. The structure-optimizing principle with the closed-loop model is corroborated by the effective spurious-noise-suppression. The lowest phase noises as low as ?100?dBc?Hz?1 at 10?kHz with corresponding RMS timing jitter of 0.67?ps are measured. This is achieved by individually inserting 100 and 120?m long single mode fiber segments into two decoupled arms, the dual-loop COEO before the optical receiver pair. The BER performance reaches a minimum with the optimized SMF segment lengths. However, the spurious peaks arise to degrade the BER performance as the phase noise and jitter are inevitably enlarged when inserting longer SMF segments. After modulating the optimized output pulse train with the pseudo-random-bit-sequence data triggered by the same COEO clock, the SNR can achieve 10.9?dB and the receiving sensitivity is ?19.2?dBm.