Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip

Mapping intellectual properties (IPs) on network-on-chip (NoC) has a notable impact on the timing, performance, and energy consumption of NoC. In this paper, we present a novel performance and power-aware task mapping technique based on mesh NoC that combines the latency constraint and branch and bound concepts. Our proposal for the definition of latency constraint helps intensify the bounds for pattern searching. With appropriate latency constraints, the best mapping solution can be achieved with less CPU time. This algorithm can be used with any NoC mesh shape. The mapping solutions are emulated on the FPGA-based NoC emulation platform. The experimental results demonstrate that the latency-constraint branch and bound technique can achieve better timing and lower energy consumption in nearly half the CPU time of the traditional branch and bound mapping algorithm.