Test structure and test method for transistor

The invention provides a test structure and a test method for a transistor. The test structure comprises a test machine table which is connected in series between the source and the drain of the transistor to be tested and is used for generating a test signal and measuring the off capacitance between the source and the drain of the transistor to be tested, a bias voltage source which is coupled with the grid of the transistor to be tested and is used for keeping the transistor to be tested in a switch-off state, and a first resistor which is connected in series between the grid of the transistor to be tested and the bias voltage source and is used for driving a test signal generated by the test machine table to flow to the source. The test method comprises the following steps: providing a transistor to be tested; arranging a test machine table between the source and the drain of the transistor to be tested; measuring the off capacitance between the source and the drain through the test machine table; coupling a bias voltage source to the grid of the transistor to be tested; connecting a first resistor in series between the grid and the bias voltage source, and driving a test signal generated by the test machine table to flow to the source. By adopting the test structure and the test method, the off capacitance of the transistor can be closer to a true value in a testing process.