Prototyping for a DDS-based I/Q reference signal generation on a capacitive sensing chip in 65nm CMOS using SystemC AMS, C HLS and VHDL

Carrier frequency principles with synchronous de-modulation offer several advantages for use in capacitive sensors, in particular with respect to suppression of external disturbers, coexistence of sensors, and capability to determine frequency-dependent changes of the capacitance/impedance. A key component in such systems is the generation of the excitation signal(s) as well as the reference signals for demodulation.This work focuses on the early functional evaluation of direct digital synthesis for such signals using a virtual prototype in SystemC AMS (IEEE 1666.1), a high-level synthesis approach based on C (ISO 9899) as well as a classic hand-written VHDL code (IEEE 1076) for a rapid prototyping setup. The methods are compared with respect to efforts and results showing the advantages and disadvantages in a qualitative fashion. The lower efforts and lower risk of errors in the code provided by high level meta modeling allows to speed up the development cycle and required application dependent adaptations of signal generation in carrier frequency based capacitive sensor front-ends.