A Novel Power Efficient 2:4 Decoder at 16nm

A huge challenge faced by this era of developing is power reduction. The low power circuit designs is a requesting issue in high performance digital frameworks, for example, microchips, DSPs and other different applications. Power and speed are the main highlights considered while comparing any circuit or design. Diminishing chip area is additionally truly impressive factor, creators need to recall when suggesting any novel design. Decoder is used for conversion of binary inputs to associated output bits in a pattern. A novel 2:4 decoder is proposed with area optimization in this paper. CMOS logic is additionally used for execution of 2:4 decoder. Delay and power is used for evaluation between the novel design and CMOS logic. The novel design of 2:4 decoder is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 0.8V.