Geometry-Aware Single-Event Enabled Compact Models for Sub-50 nm Partially Depleted Silicon-on-Insulator Technologies

A new geometry-aware single-event enabled compact model for sub-50 nm partially depleted silicon-on-insulator MOSFETs is presented. The model extends the bias-dependent single-event modeling methods with an integrated parasitic BJT using the SPICE Gummel Poon equations and parameters derived from the manufacturer’s process design kit, physical layout, and technology information. The model compares well with TCAD and test data.