REAL-TIME FPGA-BASED IMAGE RECTIFICATION SYSTEM

Image rectification is the process of transforming stereo-images as if they were captured using a canonical stereo-system. Computationally intensive tasks, like dense stereo matching, are greatly simplified if performed on rectified images. We developed an efficient pipeline hardware machine which performs realtime image rectification. The design was implemented using VHDL, thus allowing portability on many hardware platforms. The architecture was highly optimized, both in terms of time and resources needed. To increase its flexibility, the design was described based on generics (configuration parameters), which allow reconfiguring different characteristics and behaviour, such as: image size, number of precision bits, memory cache complexity. We also analyze the performance of the implemented solution on a VirtexE600 FPGA